1/4 rev. c structure silicon monolithic ic product name capacitive sensor controller for cellular phone product no BU21018MWV features 1) high- resistive sensor material 2) high speed sensing 3) 3.0 v singe power supply 4) 36ch sensors 5) 2ch reference (1ch only use is possible) 6) automatic program download function for internal cpu absolute maximum ratings (*1) this is the power dissipa tion per ic unit. reduce to 9.2 8 mw / when ta = 25 or above. operating conditions parameter symbol rating unit digital power supply dvdd 1.60 2.00 v analog power supply avdd 2.70 3.60 v operating temperature rage topr -20 85 this chip is not designed to pr otect itself against radioactive rays. parameter symbol rating unit digital applied voltage dvdd -0.5 2.5 v analog applied voltage avdd -0.5 4.5 v digital input voltage vdi -0.5 dvdd v analog input voltage vai -0.5 avdd v storage temperature range tstg -55 125 power dissipation pd 928*1 mw
2/4 rev. c electrical characteristics parameter symbol rating unit condition min typ max digital low level input voltage vil1 -0.4 - 0.25*dvdd v digital high level input voltage vih1 0.7*dvdd - dvdd+0.5 v digital low level output voltage vol1 - - vss+0.4 v i ol =2.0[ma] analog low level output voltage vol2 - - vss+0.45 v i ol =1.0[ma] analog high level output voltage voh2 ldo-0.4 - ldo+0.5 v i oh =-0.5[ma] osc frequency freq 21.0 24.0 27.0 mhz digital standby current ist1 0 - 10 ua analog standby current ist2 0 - 10 ua digital operating current idd1 - 3 5.5 ma analog operation current idd2 - 1 1.5 ma *ta = 25 as long as it doesn't specify it. block diagram cpu core program memory 16kb data memory 2kb cv transfer controller noise filter clock controller 11 12 13 20 50 51 52 sin00 sin01 sin02 sin03 sin33 sin34 sin35 reset (por) calibration controller eeprom i2c 1 10 i2c 5 6 register osc 4 8 7 adr_sel scl sda eda ecl reset ext_clk cpu core program memory 16kb data memory 2kb cv transfer controller noise filter clock controller 11 12 13 20 50 51 52 sin00 sin01 sin02 sin03 sin33 sin34 sin35 reset (por) calibration controller eeprom i2c 1 10 i2c 5 6 register osc 4 8 7 adr_sel scl sda eda ecl reset ext_clk
3/4 rev. c external measure and view pin d escription package uqfn056v7070 *1 please do not connect devic es other than BU21018MWV. pin name discription 1 extclk external clock input 2 int interrupt 3 nc - 4 sda i2c:sda 5 scl i2c:scl 6 adr_sel i2c: address select l (1011100) 2 h (1011101) 2 7 eda automatic program download of eeprom (sda) 8 ecl automatic program download of eeprom (scl) 9 ifsel interface select (low fix) 10 dvdd digital power connect to ldo pin. 11 sin00 sensor 12 sin01 sensor 13 sin02 sensor 14 ldo ldo output *1 15 vss ground 16 avdd analog power 17 reset reset l reset h release 18 sref0 reference sensor 19 sref1 reference sensor 20 sin03 sensor 21 sin04 sensor 22~50 sin05~sin33 sensor 51 sin34 sensor 52 sin35 sensor 53 test0 test (low fix) 54 test1 test (low fix) 55 test2 test (low fix) 56 test3 test (low fix) bu21018 lot no.
4/4 rev. c cautions on use (1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply volta ge, temperature range of operating conditions, etc., can break down devices, thus making impossi ble to identify breaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) operating conditions these conditions repre sent a range within which characteristics can be provided approximately as expected. the electrical characteristics are guaranteed under the conditions of each par ameter. (3) reverse connection of power supply connector the reverse connection of power supply connector can break down ics. take protective measures against the breakdown due to the reverse connection, such as m ounting an external diode b etween the power supply and the ic's power supply terminal. (4) power supply line design pcb pattern to provide lo w impedance for the wiring betw een the power supply an d the gnd lines. in this regard, for the digital block power supply an d the analog block power supply, even though these power su pplies has the same level of potential, separate the power supply pattern for the digital bl ock from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give consideration to design the patterns in a simila r manner. furthermore, for all power supply terminals to ics, mount a cap acitor between the power supply and the gnd terminal. at the same time, in order to use an el ectrolytic capacitor, thoroughl y check to be sure the characteris tics of the capacitor to be used present no problem includ ing the occurrence of capacity dr opout at a low temperature, th us determining the constant. (5) gnd voltage make setting of the potential o f the gnd terminal so that it wi ll be maintained at the mini mum in any operating state. furthermore, check to be sure no terminals are at a potential l ower than the gnd voltage including an actual electric transien t. (6) short circuit between termi nals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to t he direction and offset of the ics. erroneous mounting can break down the ics. furthermore , if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ics can break down. (7) operation in strong electromagnetic field be noted that using ics in the st rong electromagnetic field can malfunction them. (8) inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic termina l, the ic can suffer stress. therefore, be sure to discharge from the set pcb by each proces s. furthermore, in order to mount or dismount the set pcb to/from the jig for the inspection process, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power supply and then dismount it fr om the jig. in addition, for protection against static electri city, establish a ground for t he assembly process and pay thorough attention to the transportation and the st orage of the set pcb. (9) input terminals in terms of the construction of i c, parasitic elements are inev itably formed in relation to pot en tial. the operation of the parasitic element can cause in terference with circuit operation , thus resulting in a malfunct ion and then breakdown of the input terminal. therefor e, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the gnd respectively, so that any parasitic element will operate. furthermore, do not apply a voltage to th e input terminals when no power supply voltage is applied to the ic. in addition, even if the power supply voltage is applied, a pply to the input terminals a voltage lower than the power supply vo ltage or within the guaran teed value of electrical characteristics. (10) ground wiring pattern if small-signal gnd and large-cu rrent gnd are provided, it will be recommended to separate t he large-current gnd pattern from the small-signal gnd patte rn and establish a single ground at the reference point of the set pcb so that resistance to the wiring pattern and voltage fluctuations due to a large curr ent will cause no fluctuations in voltages of the small-signal gnd. pay attention not to cause fluctu ations in the gnd wiring patte rn of external parts as well. (11) external capacitor in order to use a ceramic capacit or as the external capacitor, determine the constant with consideration given to a degradation in the nominal capa citance due to dc bias and chang es in the capacitance due to temperature, etc. (12) rush current the ic with some power supplies has a capable of rush current d ue to procedure and delay at power-on. pay attention to the capacitance of the coupling condens ers and the wiring pattern w idth and routing of the powe r supply and t he gnd lines. (13) others in case of use this lsi, please peruse some other detail documents, we called, technical note, functional description, application note.
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